1. Field of the Invention
The present invention relates to a digital image processing apparatus and, more specifically, to a digital image processing apparatus arithmetically processing original image data to realized image data converting process such as gradation correction, sharpening of image quality, and image analyzing processes such as feature extraction from the image data.
2. Description of the Prior Art
A digital image processing apparatus is constituted by hardware such as an image input circuit for inputting image data, an image output circuit for outputting image data, an image memory for storing image data, a processing circuit for arithmetically processing the image data, a host CPU controlling each of these hardwares and arithmetically processing image data utilizing software, and so on. In general, the host CPU is used for the arithmetic processing only when it is difficult to carry out the arithmetic processing by processing circuits. Most of the basic processes are executed by hard logics the processing circuits. The image data are transferred between each of the hardware treating the image data at high speed. In consideration of the flexibility and expendability of the system, an image data bus is often prepared which is exclusively used for transferring image data between each of the hardware. Discrete image data are transferred on the image data bus in synchronization with a transfer clock having a constant timing.
As described above, basic arithmetic processes, which should be processed at high speed, are carried out in the processing circuits in general. The arithmetic processing of the image data is mainly divided into two cases, i.e. a case in which the output data are image data, and a case in which the output data are not image data. The former case includes an image converting process such as improving the contrast of input image data having low contrast. The latter case comprises processes such as calculating a density histogram of the input image data, calculating an area of an object of interest in the image. In the former type processing, the result of the process may be further arithmetically processed by the processing circuit. In the latter type processing, the result of the process is no longer an image data, and therefore the host CPU is in charge of the further processing of the result. The present invention relates to a structure of a processing circuit for the former type processing, namely, both input data and output data of the process are image data.
Meanwhile, image data converting process comprise a large number of processes from a relatively simple process such as evaluating a mean value of two images to a complicated process such as clearing of a dim image. It is understood that a complicated process is a combination of basic processes when we analyzed the complicated process. The most basic operations for the image data are as follows:
(1) Addition/Subtraction and Multiplication between image data and between image data and a constant
(2) Logical operation such as AND, OR and the like between image data and between image data and a constant
(3) Bit shift operation for the image data
(4) Non-linear conversion such as logarithmic conversion
The function of addition/subtraction and the logical operation are assigned to a group of circuits which is generally called an ALU (Arithmetic Logic Unit). The multiplication can be executed by combining an adding function and a bit shift function. However, recently, ICs for multiplication having the operation speed of several 10 nsec are available, and these ICs are often utilized. The non-linear conversion is executed by means of a table memory called a Look Up Table (simply referred to as LUT). More specifically, values of input data are in correspondence with address data of the table memory, and a conversion output corresponding to the input data is stored in advance in each address of the table memory. The bit shift operation can be executed by a simple gate logic, since the operation only requires shifting of bit correspondence between input and output data.
As described above, the processing circuits of a digital image processing apparatus should comprise at least an ALU, a multiplying circuit, a bit shift circuit and a LUT as most basic arithmetic operation circuits. FIG. 1 shows an example of a structure of a conventional digital image processing apparatus having these basic arithmetic circuits. Referring to the figure, an image input circuit 1 takes in image signals out of the apparatus by converting the same to a data format which can be handled in the apparatus. An image memory 2 stores image data and the stored image data are read therefrom. A plurality of image memories (2a, 2b, 2c) may be provided, if necessarily. A processing circuit 3 comprises various basic arithmetic operation circuits. In this example, it comprises a multiplying circuit 3a, an ALU 3b, a bit shift circuit 3c and a LUT 3d. An image output circuit 4 outputs data read from the image memory 2 to the outside of the apparatus. An image data bus 5 realizes image data transfer between each of the above described circuits in various combinations of the circuits, wherein buses 5a and 5b apply output data from the image input circuit 1 and from the image memory 2 to the processing circuit 3 and the image output circuit 4, and a bus 5c applies output data from the processing circuit 3 and from the image input circuit 1 to the image memory 2 and the image output circuit 4. A control operation such as switching between operation/non-operation of each circuit, designation of an output bus in the image input circuit 1 or in the image memory 2, setting of a constant in the multiplying circuit 3a, designation of a function and setting of a constant in the ALU 3b, designation of a number of stages to be shifted and of a shift direction in the bit shift circuit 3c, setting of data in a converting table of the LUT 3d, designation of an input bus to the image output circuit 4, and so on must be executed by the host CPU or by a control circuit exclusively used for this purpose. In FIG. 1, however, the circuits for these controls are omitted for the purpose of simplification.
As shown in FIG. 1, in a conventional digital image processing apparatus, arithmetic operation circuits in charge of basic operations are arranged in parallel and the input/output buses are commonly used, so that a plurality of arithmetic operation circuits can not be operated simultaneously. Let us consider a case in which a weighted mean value is evaluated between two image data X and Y with the coefficient of 7/8 and 1/8, for example. This process is realized in three frames in the image processing apparatus of FIG. 1, as shown in FIGS. 2(a).about.(c). In this example, image data X and Y to be processed are stored in the image memories 2a and 2b, with the final result being written in an image memory 2c. In the first frame, the image data X in the image memory 2a is inputted to the multiplying circuit 3a through the image data bus 5a to be multiplied by 7 with the results written in the image memory 2c through the image data bus 5c. On this occasion, a constant number is set in the multiplying circuit 3a in advance and a state is designated in which multiplication is carried out between the image data on the image data bus 5a and the constant. In the second frame, image data are read from image memories 2c and 2b to be inputted to the ALU 3b through the image data buses 5a and 5b, as shown in FIG. 2(b). Then ALU 3b is designated to execute addition between image data on the image data buses 5a and 5b, and image data corresponding to (7X+Y) is outputted onto the image data bus 5c. The result of the process is written in the image memory 2d. In the third frame, the read data from the image memory 2d is inputted to the bit shift circuit 3c through the image data bus 5a. The bit shift circuit 3c is set such that it shifts the input data to the right direction by 3 bits. Consequently, it provides an output data which is the input data divided by 8. Namely, the output data will be (7X/8+Y/8). The output data is written in the image memory 2c through the image data bus 5c. As described above, in a conventional image processing apparatus, when three arithmetic operation circuit are necessary to execute a series of processes, three frames of processes are needed even if the three operation circuits are separate circuits, and only one arithmetic operation circuit can operate in each frame. Therefore, the operation circuits can not be effectively used, and therefore the operation speed was slow. In order to reserve the original image data, a separate image memory is needed as a working memory. If a separate memory is not used, one of the two image memories for original image data must be used as the working memory. Therefore, neither operation circuits nor image memory are utilized effectively.
FIG. 3 shows an example of a structure of another digital image processing apparatus which is an improvement of the prior art shown in FIG. 1. It is different from the prior art shown in FIG. 1 in that an image data bus 50 is added to enable coupling of input/output data between each of the operation circuits. Referring to the figure, a bus 50a supplies output data from the multiplying circuit 3a to other arithmetic operation circuits(3b,3c, 3d), a bus 50b supplies output data from the ALU3b to other arithmetic operation circuits (3a, 3c, 3d), a bus 50c supplies output data from the bit shift circuit 3c to other arithmetic operation circuits (3a, 3b, 3d), and a bus 50d supplies output data from the LUT3d to other arithmetic operation circuits (3a, 3b, 3c).
Let us consider a case in which the same process as shown in FIGS. 2(a).about.(c) is effected by the image processing apparatus of FIG. 3. FIG. 4 shows the connections between these circuits in that case. The image data from the image memory 2a is inputted to the multiplying circuits 3a through the data bus 5a, multiplied by the constant 7 to be inputted to the ALU 3b through the data bus 50a. Meanwhile, the image data on the image memory 2b is directly inputted to the ALU 3b through the data bus 5b. The ALU 3b adds the two inputs and applies the result to the bit shift circuit 3c through the data bus 50b. The bit shift circuit 3c shifts the input data in the right direction by 3 bits and the obtained output data is outputted onto the data bus 5c. The image data on the data bus 5c is written in the image memory 2c as the result of the process. Thus, the process which required 3 frames in FIG. 2 (a).about.(c) can be done in 1 frame by virtue of the newly added image data bus 50. Although the structure of FIG. 3 solves the problems of the structures shown in FIG. 1, it newly provide the following problems. Namely, the number of image data buses is increased twice or more at one time; the number of input/output ports of each operation circuit is increased; the input/output control becomes troublesome due to the increase of the number of ports; and the delay time between input/output data of the whole processing circuits is not constant, since a plurality of operation circuits are arbitrarily coupled. If a new arithmetic operation circuit should be added, the number of image data buses and the number of input and output ports of each operation circuits must be increased. Therefore, it is difficult to extend the structure of FIG. 3.
In the foregoing, two structures of conventional digital image processing apparatuses having basic operation functions have been discussed. The former structure is simple but the operation circuit and image memories can not be effectively used, so that the operation speed is slow. In the latter structure, the operation circuits and image memories can be effectively used, but the image data bus becomes large, the number of input/output ports of each operation circuit is increased, and therefore the input/output control becomes troublesome. In addition, it is difficult to extend the structure, and the delay time between input/output data is not constant.